OMAP2+ Mailbox Driver
=====================

The OMAP mailbox hardware facilitates communication between different
processors using a queued mailbox interrupt mechanism. The IP block is
external to the various processor subsystems and is connected on an
interconnect bus. The communication is achieved through a set of
registers for message storage and interrupt configuration registers.

Each mailbox IP block has a certain number of h/w fifo queues and output
interrupt lines. An output interrupt line is routed to a specific interrupt
controller on a processor subsystem, and there can be more than one line
going to a specific processor's interrupt controller. The interrupt line
connections are fixed for an instance and are dictated by the IP integration
into the SoC. Each interrupt line is programmable through a set of interrupt
configuration registers, and have a rx and tx interrupt source per h/w fifo.
Communication between different processors is achieved through the appropriate
programming of the rx and tx interrupt sources on the appropriate interrupt
lines.

The number of h/w fifo queues and interrupt lines dictate the usable registers.
All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
instance. DRA7xx has multiple instances with different number of h/w fifo
queues and interrupt lines between different instances. The interrupt lines
can also be routed to different processor sub-systems on DRA7xx as they are
routed through the Crossbar, a kind of interrupt router/multiplexer.

The above two varying SoC IP integration parameters are defined specifically
through the "ti,mbox-num-users" and "ti,mbox-num-fifos" device-tree properties.
These are defined in the DT nodes since these design parameters can vary between
one instance to another in an SoC (eg: DRA7xx) even though the base IP design
is identical.

Required properties:
--------------------
- compatible:		Should be one of the following,
			    "ti,omap2-mailbox" for
				OMAP2420, OMAP2430, OMAP3430, OMAP3630 SoCs
			    "ti,omap4-mailbox" for
				OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
- reg:			Contains the mailbox register address range (base address
			and length)
- interrupts: 		Contains the interrupt information for the mailbox
			device. The format is dependent on which interrupt
			controller the OMAP device uses
- ti,hwmods:		Name of the hwmod associated with the mailbox
- ti,mbox-num-users:	Number of targets (processor devices) that the mailbox device
			can interrupt
- ti,mbox-num-fifos:	Number of h/w fifos within the mailbox device
- ti,mbox-names:	Array of the names of the mailboxes
- ti,mbox-data:		Mailbox descriptor data private to each mailbox. The 4
			cells represent the following data,
			  Cell #1 (tx_id) - mailbox fifo id used for
						transmitting messages
			  Cell #2 (rx_id) - mailbox fifo id on which messages
						are received
			  Cell #3 (irq_id) - irq identifier index number to use
						from the interrupts data
			  Cell #4 (usr_id) - mailbox user id for identifying the
						interrupt into the MPU interrupt
						controller.

Example:
--------

/* OMAP4 */
mailbox: mailbox@4a0f4000 {
	compatible = "ti,omap4-mailbox";
	reg = <0x4a0f4000 0x200>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "mailbox";
	ti,mbox-num-users = <3>;
	ti,mbox-num-fifos = <8>;
	ti,mbox-names = "mbox-ipu", "mbox-dsp";
	ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
};
