Texas Instruments K3 Interrupt Router
=====================================

The Interrupt Router (INTR) module provides a mechanism to mux M
interrupt inputs to N interrupt outputs, where all M inputs are selectable
to be driven per N output. There is one register per output (MUXCNTL_N) that
controls the selection.


                                 Interrupt Router
                             +----------------------+
                             |  Inputs     Outputs  |
        +-------+            | +------+             |
        | GPIO  |----------->| | irq0 |             |       Host IRQ
        +-------+            | +------+             |      controller
                             |    .        +-----+  |      +-------+
        +-------+            |    .        |  0  |  |----->|  IRQ  |
        | INTA  |----------->|    .        +-----+  |      +-------+
        +-------+            |    .          .      |
                             | +------+      .      |
                             | | irqM |    +-----+  |
                             | +------+    |  N  |  |
                             |             +-----+  |
                             +----------------------+

Configuration of these MUXCNTL_N registers is done by a system controller
(like the Device Memory and Security Controller on K3 AM654 SoC). System
controller will keep track of the used and unused registers within the Router.
Driver should request the system controller to get the range of GIC IRQs
assigned to the requesting hosts. It is the drivers responsibility to keep
track of Host IRQs.

Communication between the host processor running an OS and the system
controller happens through a protocol called TI System Control Interface
(TISCI protocol). For more details refer:
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt

TISCI Interrupt Router Node:
----------------------------
- compatible:		Must be "ti,sci-intr".
- interrupt-controller:	Identifies the node as an interrupt controller
- #interrupt-cells:	Specifies the number of cells needed to encode an
			interrupt source. The value should be 3.
			First cell should contain the TISCI device ID of source
			Second cell should contain the interrupt source offset
			within the device
			Third cell specifies the trigger type as defined
			in interrupts.txt in this directory. Only level
			sensitive trigger types are supported.
- interrupt-parent:	phandle of irq parent for TISCI intr.
- ti,sci:		Phandle to TI-SCI compatible System controller node.
- ti,sci-dst-id:	TISCI device ID of the destination IRQ controller.
- ti,sci-rm-range-girq:	TISCI subtype id representing the host irqs assigned
			to this interrupt router.

Example:
--------
The following example demonstrates both interrupt router node and the consumer
node(main gpio) on the AM654 SoC:

main_intr: interrupt-controller@1 {
	compatible = "ti,sci-intr";
	interrupt-controller;
	interrupt-parent = <&gic>;
	#interrupt-cells = <3>;
	ti,sci = <&dmsc>;
	ti,sci-dst-id = <56>;
	ti,sci-rm-range-girq = <0x1>;
};

main_gpio0:  main_gpio0@600000 {
	...
	interrupt-parent = <&main_intr>;
	interrupts = <57 256 IRQ_TYPE_EDGE_RISING>,
			<57 257 IRQ_TYPE_EDGE_RISING>,
			<57 258 IRQ_TYPE_EDGE_RISING>,
			<57 259 IRQ_TYPE_EDGE_RISING>,
			<57 260 IRQ_TYPE_EDGE_RISING>,
			<57 261 IRQ_TYPE_EDGE_RISING>;
	...
};
