diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index f595d812f..de88aa19b 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -64,6 +64,7 @@
 #define DPLL_FINT_INVALID		-2
 
 /* Private functions */
+extern bool omapdss_is_enable_disp_dpll_sscg(void);
 
 /*
  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
@@ -324,6 +325,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	for (n = dd->min_divider; n <= dd->max_divider; n++) {
 
+		if( omapdss_is_enable_disp_dpll_sscg() && ( n == 1 ) ) continue;
+
 		/* Is the (input clk, divider) pair valid for the DPLL? */
 		r = _dpll_test_fint(clk, n);
 		if (r == DPLL_FINT_UNDERFLOW)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index d3db4ae2b..9cf07324a 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -41,6 +41,9 @@
 #define MAX_DPLL_WAIT_TRIES		1000000
 
 /* Private functions */
+extern bool omapdss_is_enable_disp_dpll_sscg(void);
+extern unsigned long omapdss_get_ssc_deltastep(void);
+extern unsigned long omapdss_get_ssc_modfreqdev(void);
 
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
@@ -350,6 +353,53 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 
 	omap2_clk_writel(v, clk, dd->mult_div1_reg);
 
+	if( omapdss_is_enable_disp_dpll_sscg() ) {
+
+		//! ssc_deltastep
+		{
+			struct clk_omap_reg *reg;
+			u32 tmp;
+			reg = (struct clk_omap_reg *)&tmp;
+
+			reg->index = 0x0001;
+			reg->offset = 0x2800 + 0x648;
+
+			v = omapdss_get_ssc_deltastep();
+
+			if( v != omap2_clk_readl(clk, (void __iomem *)tmp) ){
+				omap2_clk_writel(v , clk, (void __iomem *)tmp);
+			}
+		}
+
+		//! ssc_modfreqdev
+		{
+			struct clk_omap_reg *reg;
+			u32 tmp;
+			reg = (struct clk_omap_reg *)&tmp;
+
+			reg->index = 0x0001;
+			reg->offset = 0x2800 + 0x64C;
+
+			v = omapdss_get_ssc_modfreqdev();
+
+			if( v != omap2_clk_readl(clk, (void __iomem *)tmp) ){
+				omap2_clk_writel(v , clk, (void __iomem *)tmp);
+			}
+		}
+
+		//! ssc enable
+		{
+			const struct dpll_data *dd;
+			u32 v;
+
+			dd = clk->dpll_data;
+
+			v = omap2_clk_readl(clk, dd->control_reg);
+			v |= 0x00001000;
+			omap2_clk_writel(v, clk, dd->control_reg);
+		}
+
+	}
 	/* Set 4X multiplier and low-power mode */
 	if (dd->m4xen_mask || dd->lpmode_mask) {
 		v = omap2_clk_readl(clk, dd->control_reg);
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index dda020cde..2c145e9e8 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -25,6 +25,8 @@
 #undef pr_fmt
 #define pr_fmt(fmt) "%s: " fmt, __func__
 
+extern bool omapdss_is_enable_disp_dpll_sscg(void);
+
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define div_mask(d)	((1 << ((d)->width)) - 1)
@@ -146,7 +148,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 {
 	struct clk_divider *divider = to_clk_divider(hw);
 	int i, bestdiv = 0;
-	unsigned long parent_rate, best = 0, now, maxdiv;
+	unsigned long parent_rate, best = 0, now, maxdiv,mindiv;
 	unsigned long parent_rate_saved = *best_parent_rate;
 
 	if (!rate)
@@ -167,8 +169,8 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 	 * unsigned long in rate * i below
 	 */
 	maxdiv = min(ULONG_MAX / rate, maxdiv);
-
-	for (i = 1; i <= maxdiv; i++) {
+	mindiv = (omapdss_is_enable_disp_dpll_sscg()) ? 2 : 1;
+	for (i = mindiv; i <= maxdiv; i++) {
 		if (!_is_valid_div(divider, i))
 			continue;
 		if (rate * i == parent_rate_saved) {
diff --git a/drivers/video/fbdev/omap2/dss/core.c b/drivers/video/fbdev/omap2/dss/core.c
index 6b74f73fb..45e4ba3ac 100644
--- a/drivers/video/fbdev/omap2/dss/core.c
+++ b/drivers/video/fbdev/omap2/dss/core.c
@@ -46,12 +46,36 @@ static struct {
 	const char *default_display_name;
 } core;
 
+static unsigned int enable_disp_dpll_sscg=1;
+module_param(enable_disp_dpll_sscg, uint, 0);
+
+static unsigned long ssc_deltastep=0x624;
+module_param(ssc_deltastep, ulong, 0);
+
+static unsigned long ssc_modfreqdev=0x64;
+module_param(ssc_modfreqdev, ulong, 0);
+
 static char *def_disp_name;
 module_param_named(def_disp, def_disp_name, charp, 0);
 MODULE_PARM_DESC(def_disp, "default display name");
 
 static bool dss_initialized;
 
+bool omapdss_is_enable_disp_dpll_sscg(void)
+{
+	return (enable_disp_dpll_sscg != 0 && dss_initialized);
+}
+
+unsigned long omapdss_get_ssc_deltastep(void)
+{
+	return ssc_deltastep;
+}
+
+unsigned long omapdss_get_ssc_modfreqdev(void)
+{
+	return ssc_modfreqdev;
+}
+
 const char *omapdss_get_default_display_name(void)
 {
 	return core.default_display_name;
